The RVSoC Project was the origin, serving as a research and development project of the RISC-V computer system targeting FPGAs in Verilog HDL at Arch Lab, Tokyo Tech. Building on this foundation, we ...
Mojo-V (pronounced “mojo-five”) is a new RISC-V extension that introduces privacy-oriented programming capabilities for RISC-V. Mojo-V implements secret computation, enabling secure, efficient, and ...
Abstract: This paper presents the implementation and verification process of a 32-bit microcontroller using the open-source RISC-V Steel 32-bit processor on the FPGA DE2 development kit and ASIC ...
Abstract: This paper presents the design and implementation of a RISC-V processor core with a single-stage architecture, focusing on the execution of the base 32I instruction set. The processor core ...