Electronics Weekly

In FPGA design timing is everything, says Synopsys

When your FPGA design fails to meet timing performance objectives, the cause may not be obvious. The solution lies not only in the FPGA implementation tools’ talent in optimising the design to meet ...
Electronic Design

Using AI to Design FPGA-Based Solutions

What’s new in Xilinx’s FPGA design tool? How machine learning is employed by the design tool. What’s the difference between using AI in the tool and creating a solution that uses AI? Xilinx takes ...
EDN

Xilinx Delivers First Public Access Release of its Next-Generation Vivado Design Suite

Given the size and complexity of today's designs, developers face multidimensional design challenges that prevent them from achieving automated design closure. The Vivado Design Suite 2012.2 place and ...
Design-Reuse

Xilinx Accelerates Productivity for Zynq-7000 All Programmable SoCs with the Vivado Design Suite 2014.3, SDK, and New UltraFast Embedded Design Methodology Guide

SAN JOSE, Calif. -- Oct. 8, 2014 -- Xilinx, Inc. (NASDAQ: XLNX) today announced major advances in productivity for Zynq®-7000 All Programmable SoCs with the Vivado® Design Suite 2014.3, the ...
Electronics Weekly

Xilinx adds machine learning optimisation to Vivado to accelerate design cycle

Claiming to be able to reduce design compile times by a factor of five, Xilinx has launched the Vivado ML Editions tool suite. The latest addition to the company’s Vivado tool suite is believed to be ...
EDN

Xilinx Unveils the Vivado Design Suite for the Next Decade of ‘All Programmable’ Devices

SAN JOSE, Calif., April 24, 2012 /PRNewswire/ — Xilinx, Inc. (NASDAQ: XLNX) today announced the Vivado™ Design Suite, a new IP and system-centric design environment built from the ground up to ...
Hackaday

Parallel Programming For FPGAs

One of the best features of using FPGAs for a design is the inherent parallelism. Sure, you can write software to take advantage of multiple CPUs. But with an FPGA you can enjoy massive parallelism ...