Semiconductor wafer defect pattern recognition and classification is a crucial area of research that underpins yield enhancement and quality assurance in microelectronics manufacturing. The discipline ...

Detecting macro-defects early in the wafer processing flow is vital for yield and process improvement, and it is driving innovations in both inspection techniques and wafer test map analysis. At the ...

Defect detection requirements on the order of 10 defective parts per million (DPPM) are driving improvements in inspection tools’ resolution and throughput at foundries and OSATs. However, defects ...

During lapping, a spinning abrasive surface is used to thin wafers from the backside. As the process progresses, precise feedback is required to monitor the amount of material removed and determine ...

The global integrated circuit (IC) industry is confronting the physical limitations of Moore's Law. Atomic-layer-thick two-dimensional (2D) semiconductors, such as Molybdenum Disulfide (MoS2), are ...