Semiconductor Engineering

In-SRAM Computing Architecture Tailored For Cryptographic Acceleration Within MCUs (UC Riverside)

A new technical paper titled “CryptoSRAM: Enabling High-Throughput Cryptography on MCUs via In-SRAM Computing” was published by researchers at University of California, Riverside. “Secure ...
Semiconductor Engineering

An Energy-Efficient 10T SRAM In-Memory Computing Macro Architecture For AI Edge Processor

A technical paper titled “An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processor” was published by researchers at Atal Bihari Vajpayee-Indian Institute of ...
Design-Reuse

Dolphin Integration unveils an sRAM architecture for Cost Sensitive Devices at 90 nm LP

Grenoble, France – December 16, 2011. Dolphin Integration is releasing RHEA, the latest innovation of the sRAM family, for cost sensitive SoCs at 90 nm and 85 nm TSMC technological processes. In ...