Virage Logic Corp. announced a silicon and volume production-proven 40-nm G PCI Express Gen1/Gen2 Physical Layer (PHY) IP block. The SiPro PCI Express PHY product line represents the first offering in ...
SAN FRANCISCO-- July 28, 2009 --Virage Logic Corporation (NASDAQ:VIRL), the semiconductor industry's trusted IP partner, today announced its new offering, a silicon and volume production-proven ...
The LMK00338 is an 8-output PCIe Gen1/Gen2/Gen3 fanout buffer intended for high-frequency, low-jitter clock/data distribution and level translation. The input clock can be selected from two universal ...
A new 3U OpenVPX PCI Express and Ethernet hybrid switch has been designed to provide 10 times the I/O bandwidth of current systems, paving the way for a new generation of high performance embedded ...
Scope maker LeCroy has introduced PCI Express Gen 1.x, 2.0 and 3.0 decode annotation for validation and debug, adding protocol awareness to its physical layer tools. “Hardware and system engineers can ...
Designers now have access to silicon and volume production-proven 40-nm G PCI Express Gen1/Gen2 Physical Layer (PHY) intellectual property (IP). The SiPro PCI Express PHY product line is the first ...
PCI-SIG, the organization in charge of maintaining and developing PCI-Express, has announced that the third version of the PCIe standard is finished and ready for implementation. The new standard is ...
PCI-Express (PCIe) is the backbone of today’s complex systems requiring high speed data communication with high throughput. It is being used extensively in different applications like computer cards, ...
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